Before continue we have to edit some configuration in the Zynq, this configuration are important for set I/O peripherals and correct clock value which are necessary for the Zybo correct function at least with this hardware specification, double click on Zynq7 IP then click on Import XPS Settings then look for the settings file and press ok. we almost done now we have to set constraint.
Before set constraints we are going to configure AXI GPIO IP since this IP has 32 bits width we have 32 possible signals, you have to think how many signals you need and then set the new width, do double click on AXI GPIO IP and set GPIO width to 8 for this example all bits are input and output and also we do not enable dual channel, Figure 8 shows the result
Now we have to create the wrapper file which is the main vhdl entity defined starting from our block design; right click over our block design in design sources folder at the sources panel select Create HDL Wrapper from context menu, the wrapper file appeards in the sources panel containing the block design.
If you do double click on the wrapper file you will see the entity defined in vhdl, Figure 9 shows this entity. It is possible to see the STD_LOGIC_VECTOR defining the signals for the AXI GPIO IP, note that this STD_LOGIC_VECTOR is 8 bits width.
We are going to use this vector to connect GPIO pins with Zybo PMOD pins and this is possible mapping the vector with those pins in the constraints file.
You have to have the constraints file ready to load, go to the sources panel right click on Constraints folder choose Add sources from the new window choose Add or create constraints click on next, add file, localize the .xdc file and open.
Now if you do double click over constraint files we are going to see all the possible pins that we can map with our signals. At this point we have to uncomment the lines corresponding to used pins and rename the used signals according to our project, our pins are all Pmod JE (Standard) so we have to look for them on the file. use find function (ctrl+f) and write Header JE
Now we are going to replace default signal name for our AXI_GPIO signals, when we generate the wrapper these signals become a STD_LOGIC_VECTOR with gpio_rtl_tri_io as a name you can see this int the last line of the entity definition in the axi_gpio_example_wrapper.vhd, edit each signal with the new name.
Its important to be aware that these steps are always necessary when you are working with the PL part of the SoC it could vary about the constraints but always is necessary to configure the Zynq IP and any IP that we are using.
We are ready to generate the bitstream which is the hardware definition bit format to load in FPGA each bitstream is specific for arquitecture and the size is always the same. In order to create it we have to synthetize and implement our design we can run each process separately or press on Generate Bitstream button if we are only interesting in generate it, we can generate bitstream by pressing on the button at the left panel in Vivado, this process might take some time.
When the process is finished we can upload the bitstream to the FPGA, by pressing on hardware manager button at the left panel we configure the hardware target which is the zybo board.
Connect the board to the computer an turn it on and press over program device button at the top of the main panel, also upload the bitstream is a process that can be done in with Xilinx SDK.
After generate bitstream we are going to test our peripherals by using test program on Vivado SDK but before launch we have to export the hardware, go to menu and select File>Export>Export Hardware the launch SDK go to File>Launch SDK
In Xilinx SDK go to File>new>Application project give a name and keep all the option with default value (assure that the C option is selected) press next and in the available Templates choose Peripheral Tests
Now we have the test ready this project test all the peripherals in the hardware, go to the project explorer and right click on the project test and choose Run As>Launch on Hardware (GDB), if you have configure a terminal you can see the result wrote in it, yo can use the Xilinx SDK default terminal but you need to configure it. We are going to do this in the next part.