Using Standard Pmod in Zybo Zynq-7000 Development Board – Part 1

Objetives:

  • To show hardware configuration which is needed to access Pmod connectors in the Zybo Board
  • To make an application using Xilinx SDK which is allowed control external LEDs connected to the standard PMOD (JE) using el BTN0 (R18)

Tools:

You are going to need:

  • Vivado
  • Xilinx SDK

Main steps:

  • Create new project
  • Create block design
  • Configure IPs
  • Set constraints
  • Program software

Content:

The Zybo Board has six PMOD connectors, JF PMOD connectors is mapped directly to the PS that mean it can be used directly with the MIO interfaces, the rest of them have to be accessed using AXI Bus because they are in the PL space:

Pmod_pinout

In this practice is used the standard PMOD (JE PMOD). the pin map is summarised in the penultimate column in Figure 1, to probe this we are going to develop the next hardware:

Screen Shot 2014-10-19 at 1.34.12 AM

As the reader is aware, the Zynq is connected with the respective interfaces to IP AXI GPIO this allows Zynq to communicate with the PL through the AXI Bus. In order to prepare this hardware, we have to do the next step:

1. Create a project in Vivado selecting the destination folder, the name and all the option needed (Figure 2).

2. On the workspace, go to the left panel and create a block design using “Create Block Design” (Figure 3).

vivadoScreen

3. Using the auxiliary panel search for “ZYNQ7 Processing System” and wait for a while (Figure 4).

addIPP

4. Again using the auxiliary panel search for “AXI GPIO” IP, after this you will have a design like in the Figure 5.

axi_GPIO_IP

5. Click on “Run Block Automation” in the Designer Assistance and press ok in the window showed (Figura 6).

run_block_automation

6. As a previous step go to the Designer Assistance and click on “Run Connection Automation”, you have to do this two time in order to create the connection between Slave AXI interface (S_AXI) in AXI the GPIO IP and expand the GPIO port in the same IP, after that you will have a design like Figure 7.

full_design

By this step it has appeared two blocks in the design, for this article you don’t need to know about them, I just mention to you that these are necessary for communicate PS with the peripherals in the PL through AXI Bus, but this is not going to explain here.

The hardware is almost ready, the next steps is create a constraint file which contains the information about the port mapped to specific pins in the PL, these pins could be switches, buttons, LEDs or PMOD ports which is our objective, so lets finish the hardware design with the next part of the article

Go to Part two

 

 

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