PCBs Design An Introduction | Diseño de PCBs una Introducción – Spanish



  • Document is not complete yet
  • Document is only writen in Spanish by now

This document was used for training in the PCBs design topic. It uses the next software:

  • Autodesk Eagle
  • FlatCAM 8.5

Covered topics include:

  • Schematic and PCB board design using Eagle.
  • Generate output file such as Gerber and CNC jobs using Eagle and FlatCAM 8.5.
  • Electronic review for beginners (Optional reading)
  • Export design to mechanical CAD software using Fusion 360.

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  • El documento no esta completo

Este documento fue usado para entrenamiento en el diseño de PCBs. Usa el siguiente software:

  • Autodesk Eagle
  • FlatCAM 8.5

Topicos cubiertos incluyen:

  • Esquemáticos y diseño PCBs board usando Eagle.
  • Generar archivos resultantes tales como Genber y CNC jobs usando Eagle y FlatCAM 8.5
  • Revision de conceptos de electrónica para principiantes (lectura opcional)
  • Esportar diseño hacia software CAD de diseño mecánico usando Fusion 360.

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Linux Device Driver An Introduction with Raspberry Pi | Introducción a Driver de Linux con Raspberry Pi


This document was used in the COMPDES2017 for training purpose. The main details you must know about this document are:

  1. Many aspects are no cited in the document because it was given during the training sessions, I will complete as soon as I can.
  2. It’s written only in Spanish because the event (COMPDES) is for Latin America students, I will release the English version soon.

The purpose of this document is giving a source where you can find useful information and understand Linux Device Driver. However, the best document to study this theory, in my opinion is Linux Device Driver by Jonathan Corbet. I wrote theory supported by examples. There is a framework with instructions to prepare an environment, and you can test examples. Despite the fact the document is Raspberry Pi-focused as hardware for this training, many theory aspects apply to others scenarios.

I recommend you try to understand memory address management (virtual and physical addresses) that is one of the most useful topics about communication between Kernel operative system and hardware peripheral.

Hope you can find useful information in this document.

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Este documento fue usado en el COMPDES2017 en un taller para entrenamiento. Los principales detalles que debes saber sobre este documento son:

Muchos aspectos no estan citados en el documento porque fueron discutidos durante las sesiones del taller; las completaré tan pronto como pueda.
Esta escrito solamente en español pues el evento (COMPDES) es para estudiantes de latino america; escribiré la versión en Ingles pronto.

El propósito de este documento es ofrecer una fuente donde puedas encontrar informaion útil y entender mas acerca de Linux Device Driver. Sin embargo, el mejor documento para estudiar esta teoría, en mi opinión es Linux Device Driver by Jonathan Corbet. Escribí teoría para apoyada con ejemplos. Existe un framework con instrucciones para preparar un entorno, y poder probar ejemplos. A pesar del hecho que el documento esta enfocado a Raspberry Pi como hardware para este estudio, muchos aspectos teoricos aplican para otros escenarios.

Recomiendo que intentes ententer la administración de direcciones de memoria (direcciones físicas y virtuales) que es uno de los topicos mas útiles sobre comunicación entre Kernel de sistema operativo y perifericos de hardware.

Espero puedas encontrar informacion útil en este documento.

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Using Standard Pmod in Zybo Zynq-7000 Development Board – Part 2

Go to Part one

Before continue we have to edit some configuration in the Zynq, this configuration are important for set I/O peripherals and correct clock value which are necessary for the Zybo correct function at least with this hardware specification, double click on Zynq7 IP then click on Import XPS Settings then look for the settings file and press ok. we almost done now we have to set constraint.


Before set constraints we are going to configure AXI GPIO IP since this IP has 32 bits width we have 32  possible signals, you have to think how many signals you need and then set the new width, do double click on AXI GPIO IP and set GPIO width to 8 for this example all bits are input and output and also we do not enable dual channel, Figure 8 shows the result



axi gpio configuration

Now we have to create the wrapper file which is the main vhdl entity defined starting from our block design; right click over our block design in design sources folder at the sources panel select Create HDL Wrapper from context menu, the wrapper file appeards in the sources panel containing the block design.

If you do double click on the wrapper file you will see the entity defined in vhdl, Figure 9 shows this entity. It is possible to see the STD_LOGIC_VECTOR defining the signals for the AXI GPIO IP, note that this STD_LOGIC_VECTOR is 8 bits width.

main entity

We are going to use this vector to connect GPIO pins with Zybo PMOD pins and this is possible mapping the vector with those pins in the constraints file.

You have to have the constraints file ready to load, go to the sources panel right click on Constraints folder choose Add sources from the new window choose Add or create constraints click on next, add file, localize the .xdc file and open.


Now if you do double click over constraint files we are going to see all the possible pins that we can map with our signals. At this point we have to uncomment the lines corresponding to used pins and rename the used signals according to our project, our pins are all Pmod JE (Standard) so we have to look for them on the file. use find function (ctrl+f) and write Header JE


Now we are going to replace default signal name for our AXI_GPIO signals, when we generate the wrapper these signals become a STD_LOGIC_VECTOR with gpio_rtl_tri_io as a name you can see this int the last line of the entity definition in the axi_gpio_example_wrapper.vhd, edit each signal with the new name.


Its important to be aware that these steps are always necessary when you are working with the PL part of the SoC it could vary about the constraints but always is necessary to configure the Zynq IP and any IP that we are using.

We are ready to generate the bitstream which is the hardware definition bit format to load in FPGA each bitstream is specific for arquitecture and the size is always the same. In order to create it we have to synthetize and implement our design we can run each process separately or press on Generate Bitstream button if we are only interesting in generate it, we can generate bitstream by pressing on the button at the left panel in Vivado, this process might take some time.

When the process is finished we can upload the bitstream to the FPGA, by pressing on hardware manager button at the left panel we configure the hardware target which is the zybo board.


Connect the board to the computer an turn it on and press over program device button at the top of the main panel, also upload the bitstream is a process that can be done in with Xilinx SDK.


After generate bitstream we are going to test our peripherals by using test program on Vivado SDK but before launch we have to export the hardware, go to menu and select File>Export>Export Hardware the launch SDK go to File>Launch SDK

In Xilinx SDK go to File>new>Application project give a name and keep all the option with default value (assure that the C option is selected) press next and in the available Templates choose Peripheral Tests 


Now we have the test ready this project test all the peripherals in the hardware, go to the project explorer and right click on the project test and choose Run As>Launch on Hardware (GDB), if you have configure a terminal you can see the result wrote in it, yo can use the Xilinx SDK default terminal but you need to configure it. We are going to do this in the next part.

Using Standard Pmod in Zybo Zynq-7000 Development Board – Part 1


  • To show hardware configuration which is needed to access Pmod connectors in the Zybo Board
  • To make an application using Xilinx SDK which is allowed control external LEDs connected to the standard PMOD (JE) using el BTN0 (R18)


You are going to need:

  • Vivado
  • Xilinx SDK

Main steps:

  • Create new project
  • Create block design
  • Configure IPs
  • Set constraints
  • Program software


The Zybo Board has six PMOD connectors, JF PMOD connectors is mapped directly to the PS that mean it can be used directly with the MIO interfaces, the rest of them have to be accessed using AXI Bus because they are in the PL space:


In this practice is used the standard PMOD (JE PMOD). the pin map is summarised in the penultimate column in Figure 1, to probe this we are going to develop the next hardware:

Screen Shot 2014-10-19 at 1.34.12 AM

As the reader is aware, the Zynq is connected with the respective interfaces to IP AXI GPIO this allows Zynq to communicate with the PL through the AXI Bus. In order to prepare this hardware, we have to do the next step:

Contine reading